Verilog Timing Controls

// Time units (set with `timescale)
`timescale 1ns/1ps
initial begin
    #10 a = 1;           // Wait 10ns, then assign
    #5  b = 0;           // Wait 5ns more (15ns total)
    #0  c = 1;           // Zero delay (end of current time step)
end
// Intra-assignment delay
assign #5 y = a & b;     // Output delayed 5ns from input change
// Multiple delays in one statement
initial begin
    a = #10 1;           // Evaluate 1 now, assign after 10ns
    b = #5  2;           // Evaluate 2 now, assign after 5ns
end

// Wait for any change
always @(a or b or c)  // Old style
always @(*)            // Verilog-2001 (all signals)
// Wait for specific edge
always @(posedge clk)        // Rising edge
always @(negedge clk)        // Falling edge
always @(posedge clk or negedge rst_n)  // Multiple edges
// Testbench usage
initial begin
    @(posedge clk);          // Wait for rising edge
    data = 8'hAB;
    @(posedge clk);          // Wait for next rising edge
    data = 8'hCD;
end
// Wait for signal to be high
initial begin
    @(posedge valid);        // Wait for valid to go high
    captured_data = data;
end

initial begin
    wait (reset == 0);       // Wait for reset to deassert
    $display("Reset done!");
    wait (fifo_empty == 0);  // Wait for FIFO to have data
    read_data = fifo_data;
end
// Combining wait with event
initial begin
    wait (enable);           // Wait for enable = 1
    @(posedge clk);          // Then wait for clock edge
    start <= 1;
end

// Format: `timescale time_unit/time_precision
`timescale 1ns/1ps    // Unit=1ns, precision=1ps
// Examples
`timescale 1ns/1ns    // 1ns resolution
`timescale 1ps/1ps    // Picosecond resolution
`timescale 10ns/1ns   // #1 = 10ns, precision 1ns
initial begin
    #10;    // 10 * 1ns = 10ns delay
    #0.5;   // 0.5ns (rounded to nearest ps)
end