Verilog Operators

In software (like Python or C++), an operator like + is just a command for the CPU. In Verilog, it's very different.

Think of operators as Physical Gears. When you type a + b, you are telling the computer to build a real, physical "Adder" circuit made of transistors and copper wires.

This is the #1 mistake beginners make. Let's use the Light Switch analogy:

• Logical (&&, ||): This is like asking a single question about the whole room. "Is the light on?" The answer is always 1 (Yes) or 0 (No).
• Bitwise (&, |): This is like having a Panel of 8 Switches. You look at Switch #1 on Panel A and Switch #1 on Panel B, then decide the result for Switch #1 of the Output. You do this for every switch independently.

If you use && when you meant &, you might accidentally turn on the whole room when you only wanted to flip one switch!

The operator result = (sel) ? a : b; is a Traffic Controller.

Imagine a road that splits into two. The "Traffic Controller" (the sel signal) stands at the split.

• If sel is 1, he waves the cars from Road A through to the destination.
• If sel is 0, he waves the cars from Road B through instead.

This is the most common way to make decisions in hardware (this circuit is called a Multiplexer or MUX).

Verilog handles math very similarly to other languages, but remember that every sum or product you calculate creates a real physical circuit.

wire [7:0] a = 8'd15;
wire [7:0] b = 8'd4;
wire [7:0] sum  = a + b;   // 19
wire [7:0] diff = a - b;   // 11
wire [15:0] prod = a * b;  // 60 (wider result!)
wire [7:0] quot = a / b;   // 3
wire [7:0] rem  = a % b;   // 3

Bitwise operators perform operations on each bit independently:

wire [3:0] a = 4'b1100;
wire [3:0] b = 4'b1010;
wire [3:0] inv   = ~a;       // 0011
wire [3:0] and_r = a & b;    // 1000
wire [3:0] or_r  = a | b;    // 1110
wire [3:0] xor_r = a ^ b;    // 0110
// Common use: masking
wire [7:0] data = 8'hAB;
wire [7:0] masked = data & 8'h0F;  // Keep lower nibble: 0x0B

Logical operators treat the entire operand as true (non-zero) or false (zero):

wire [3:0] a = 4'b1100;  // Non-zero (true)
wire [3:0] b = 4'b0000;  // Zero (false)
// Logical operators: 1-bit result
wire log_not = !a;       // 0 (a is non-zero, so NOT gives 0)
wire log_and = a && b;   // 0 (true AND false = false)
wire log_or  = a || b;   // 1 (true OR false = true)
// Bitwise operators: multi-bit result
wire [3:0] bit_not = ~a; // 4'b0011
wire [3:0] bit_and = a & b; // 4'b0000

Reduction operators apply a bitwise operation across all bits of a single operand, producing a 1-bit result:

wire [7:0] data = 8'b10110100;
// Check if all bits are 1
wire all_ones = &data;       // 0 (not all 1s)
// Check if any bit is 1
wire any_one = |data;        // 1 (some bits are 1)
// Parity calculation (odd number of 1s = 1)
wire parity = ^data;         // 0 (even parity)
// Check if data is zero
wire is_zero = ~|data;       // 0 (data is not zero)

1. What's the difference between & and &&?

   & is bitwise AND (multi-bit result); && is logical AND (1-bit result).

2. How do you calculate parity of a bus?

   Use the reduction XOR operator: ^bus

3. How do you check if a value is zero?

   Use reduction NOR: ~|value returns 1 if all bits are 0.