SystemVerilog Interview Questions
Comprehensive collection of SystemVerilog interview questions arranged by topic.
Top SystemVerilog Interview Traps
SystemVerilog interviews focus heavily on Object Oriented Programming (OOP) and Constrained Randomization. A common trap is assuming SV is just "Verilog with Classes". It's a completely different mindset.
Key Areas to Master:
- Deep vs Shallow Copy: This is asked in almost every interview. Know how `new` only copies the handle, not the object.
- Polymorphism: Understand how `virtual` functions behave in child classes vs parent handles.
- Race Conditions: Be ready to explain the stratified event queue (Active vs Observed vs Re-Active regions).
OOP Concepts
Classes, Inheritance, Polymorphism, Static vs Dynamic.
Data Types
Logic vs Reg, Queues, Arrays, Structs, Enum.
Threads & IPC
Fork-join, Mailboxes, Semaphores, Events.
Scheduling
Stratified Event Queue, Regions, Race Conditions.
Clocking & Interfaces
Clocking Blocks, Skews, Modports, Virtual Interfaces.
Randomization
Constraints, Solve Before, Dist, Randcase.
Assertions (SVA)
Immediate vs Concurrent, Sequences, Properties.
Functional Coverage
Covergroups, Bins, Cross Coverage, Sampling.