Parameters can be overridden during module instantiation:
Parameterized FIFO
module fifo #(
parameter DATA_WIDTH = 8,
parameter DEPTH = 16,
parameter ADDR_WIDTH = $clog2(DEPTH) // Derived parameter
) (
input wire clk,
input wire rst_n,
input wire wr_en,
input wire rd_en,
input wire [DATA_WIDTH-1:0] wr_data,
output reg [DATA_WIDTH-1:0] rd_data,
output wire full,
output wire empty
);
reg [DATA_WIDTH-1:0] mem [0:DEPTH-1];
reg [ADDR_WIDTH:0] count; // Extra bit for full detection
// ... FIFO logic
endmodule
// Instantiation with parameter override
fifo #(
.DATA_WIDTH (32),
.DEPTH (64)
) u_fifo_32x64 (
.clk (clk),
.rst_n (rst_n),
// ...
);