Synthesis Guidelines

Synthesis converts RTL to gate-level netlist. Not all Verilog constructs are synthesizable.

Synthesizable vs Non-Synthesizable

Synthesizable	NOT Synthesizable
`always @(posedge clk)`	`#delay`, `wait`
`assign`, operators	`initial` block
`if-else`, `case`	`$display`, file I/O
`for` (constant bounds)	`forever`, `while`
Functions (no timing)	Tasks with timing

Common Pitfalls

Latch Inference (BAD)

// Creates unintended latch!
always @(*) begin
    if (enable)
        result = data;
    // Missing else!
end
// FIXED:
always @(*) begin
    result = 8'd0;  // Default
    if (enable)
        result = data;
end

Blocking in Sequential (BAD)

// Wrong: blocking in sequential
always @(posedge clk) begin
    a = b;  // BAD!
    c = a;
end
// Correct: non-blocking
always @(posedge clk) begin
    a <= b;
    c <= a;
end

Interview Questions

What causes latch inference?
Incomplete assignments in combinational blocks.
Are delays synthesizable?
No. Use clock-based timing instead.
What's the synthesis result of a for loop?
Unrolled parallel hardware when bounds are constant.

Previous Behavioral Modeling