UVM Overview
Comprehensive UVM Interview Questions arranged by topic.
How to Crack the UVM Interview
The Golden Rule: Interviewers don't care if you memorized the `uvm_driver` class definition. They care if you understand how components talk to each other.
What Interviewers Look For:
- Phasing Understanding: Do you know why the build phase is top-down but connect is bottom-up? (Hint: To create children before connecting them).
- Factory Usage: Can you explain why we use `type_id::create()` instead of `new()`? (For overrides).
- TLM Basics: Difference between `blocking_put` and `nonblocking_put`.
UVM Interview Topics
Phasing
Build, Connect, Run, and Extraction phases.
Components
Agents, Drivers, Monitors, Scoreboards.
Config DB
Configuration database, set/get, precedence.
Factory
Overrides, Object creation, Registration.
Sequences
Arbitration, Virtual Sequences, Handshake.
TLM & Analysis
Ports, Exports, FIFOs, Analysis ports.
RAL (Registers)
Register Model, Frontdoor, Backdoor, Adapter.
Reporting
Verbosity, Actions, Macros.