Verilog Generate Blocks

module ripple_adder #(
    parameter WIDTH = 8
) (
    input  wire [WIDTH-1:0] a, b,
    input  wire             cin,
    output wire [WIDTH-1:0] sum,
    output wire             cout
);
    wire [WIDTH:0] carry;
    assign carry[0] = cin;
    assign cout = carry[WIDTH];
    genvar i;
    generate
        for (i = 0; i < WIDTH; i = i + 1) begin : fa_stage
            full_adder fa (
                .a    (a[i]),
                .b    (b[i]),
                .cin  (carry[i]),
                .sum  (sum[i]),
                .cout (carry[i+1])
            );
        end
    endgenerate
endmodule

module fifo #(
    parameter DEPTH = 16,
    parameter USE_BRAM = 1  // 1=BRAM, 0=distributed RAM
) (
    input  wire clk,
    // ... other ports
);
    generate
        if (USE_BRAM) begin : bram_impl
            // Instantiate Block RAM
            bram_fifo #(.DEPTH(DEPTH)) fifo_mem (...);
        end else begin : dist_impl
            // Use distributed RAM (flip-flops)
            reg [7:0] mem [0:DEPTH-1];
            // ... logic
        end
    endgenerate
endmodule

module multiplier #(
    parameter IMPL_TYPE = 0  // 0=sequential, 1=parallel, 2=DSP
) (
    input  wire [15:0] a, b,
    output wire [31:0] product
);
    generate
        case (IMPL_TYPE)
            0: begin : seq_mult
                // Sequential multiplier (small, slow)
                seq_multiplier mult (...);
            end
            1: begin : par_mult
                // Parallel multiplier (large, fast)
                parallel_multiplier mult (...);
            end
            2: begin : dsp_mult
                // DSP block multiplier
                dsp_multiplier mult (...);
            end
        endcase
    endgenerate
endmodule