Verilog Assign Statement

The assign statement creates continuous assignments that model combinational logic. It's one of the most fundamental constructs in Verilog.

Basic Syntax

The assign statement continuously drives a wire with an expression:

Assign Statement Examples

module logic_gates (
    input  wire a, b, c,
    output wire and_out,
    output wire or_out,
    output wire xor_out,
    output wire mux_out
);
    // Simple logic gates
    assign and_out = a & b;
    assign or_out  = a | b;
    assign xor_out = a ^ b;
    // Ternary operator for mux
    assign mux_out = c ? a : b;  // if c=1, output a; else b
endmodule

Key characteristics of continuous assignment:

LHS must be a wire (or other net type)
Executes continuously – output updates whenever inputs change
Models combinational logic only

Complex Expressions

Complex Assign Statements

module alu_simple (
    input  wire [7:0]  a, b,
    input  wire [1:0]  op,
    output wire [7:0]  result,
    output wire        zero,
    output wire        carry
);
    // Nested ternary for ALU
    assign result = (op == 2'b00) ? a + b :
                    (op == 2'b01) ? a - b :
                    (op == 2'b10) ? a & b :
                                    a | b;
    // Reduction operator for zero flag
    assign zero = ~|result;  // All bits zero?
    // 9-bit add for carry detection
    wire [8:0] sum_full;
    assign sum_full = a + b;
    assign carry = sum_full[8];
endmodule

Assign vs Always Block

Both can model combinational logic, but have different use cases:

Use `assign` when...	Use `always @(*)` when...
Simple, single-line expressions	Complex multi-line logic
Driving wire outputs	Need if-else or case statements
Gate-level style code	Behavioral style code

Equivalent Implementations

// Using assign
wire [7:0] y;
assign y = sel ? a : b;
// Using always (equivalent)
reg [7:0] y;  // Note: reg for always block
always @(*) begin
    if (sel)
        y = a;
    else
        y = b;
end

Common Patterns

Common Assign Patterns

// Bit selection
assign bit_3 = data[3];
// Part selection
assign lower_byte = data[7:0];
// Concatenation
assign full_word = {upper, lower};
// Replication
assign all_ones = {8{1'b1}};
// Arithmetic operations
assign sum = a + b;
assign diff = a - b;
// Tri-state buffer
assign bus = enable ? data_out : 8'bz;

Common Interview Questions

Can you use assign with reg?
No. The LHS of assign must be a net type (wire, tri, etc.), not a variable (reg).
What happens if two assigns drive the same wire?
Multi-driver conflict results in X (unknown) in simulation. Use tri-state or wired-AND/OR for intentional multi-driver scenarios.
Is assign synthesizable?
Yes, assign always synthesizes to combinational logic.

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