Gate-Level Modeling

module gates_example (
    input  wire a, b, c,
    output wire y1, y2, y3
);
    // Basic gates (output first, then inputs)
    and  g1 (y1, a, b);         // y1 = a AND b
    or   g2 (y2, a, b, c);      // y2 = a OR b OR c (multi-input)
    nand g3 (y3, a, b);         // y3 = NOT(a AND b)
    // Multiple outputs from one gate type
    not (out1, in1), (out2, in2);  // Two inverters
endmodule

module full_adder_gate (
    input  wire a, b, cin,
    output wire sum, cout
);
    wire w1, w2, w3;
    // Sum = a XOR b XOR cin
    xor g1 (w1, a, b);
    xor g2 (sum, w1, cin);
    // Cout = (a AND b) OR (cin AND (a XOR b))
    and g3 (w2, a, b);
    and g4 (w3, w1, cin);
    or  g5 (cout, w2, w3);
endmodule

// Single delay (rise = fall = turnoff)
and #5 g1 (y, a, b);  // 5 time units delay
// Rise and fall delays
and #(3, 5) g2 (y, a, b);  // Rise=3, Fall=5
// Rise, fall, and turn-off delays
bufif1 #(2, 3, 4) g3 (y, a, en);  // Rise=2, Fall=3, Turnoff=4
// Min:typ:max delays
and #(2:3:4, 3:4:5) g4 (y, a, b);  // For different timing corners

// bufif1: output = input when control = 1, else Z
bufif1 (out, in, enable);
// bufif0: output = input when control = 0, else Z
bufif0 (out, in, enable_n);
// notif1, notif0: inverted versions
notif1 (out, in, enable);   // out = ~in when enable=1
// Practical bus example
wire [7:0] bus;
bufif1 b0 (bus[0], data[0], oe);
bufif1 b1 (bus[1], data[1], oe);
// ...