Verilog System Tasks & Functions

initial begin
    // $display - print with newline
    $display("Hello World");
    $display("Value = %d (decimal)", 42);
    $display("Value = %h (hex)", 8'hAB);
    $display("Value = %b (binary)", 4'b1010);
    // $write - print without newline
    $write("Part 1 ");
    $write("Part 2\n");
    // $strobe - print at end of time step (after all assignments)
    $strobe("Strobed value = %d", count);
    // Format specifiers
    // %d - decimal    %h - hex      %b - binary
    // %o - octal      %s - string   %t - time
    // %0d - no leading zeros
end

initial begin
    // Enable monitoring (only ONE active at a time)
    $monitor("Time=%0t a=%b b=%b y=%b", $time, a, b, y);
    // Disable monitoring temporarily
    $monitoroff;
    // Re-enable
    $monitoron;
end
// Output example:
// Time=0 a=0 b=0 y=0
// Time=10 a=1 b=0 y=0
// Time=20 a=1 b=1 y=1

`timescale 1ns/1ps
initial begin
    #100.5;
    $display("$time     = %0d", $time);      // 100 (integer, units)
    $display("$stime    = %0d", $stime);     // 100 (32-bit)
    $display("$realtime = %0f", $realtime);  // 100.500000 (real)
end
// Timing checks
time start_time, end_time;
initial begin
    start_time = $time;
    #500;
    end_time = $time;
    $display("Elapsed: %0t", end_time - start_time);
end

integer seed = 12345;  // Optional seed
initial begin
    // Basic random (32-bit signed)
    $display("%d", $random);
    // With seed for repeatability
    $display("%d", $random(seed));
    // Constrained random (0 to N-1)
    $display("%d", $random % 100);      // 0-99
    $display("%d", {$random} % 100);    // 0-99 (unsigned)
    // Random in range [min, max]
    $display("%d", min + {$random} % (max - min + 1));
end
// Practical example: random delays
always @(posedge clk) begin
    #({$random} % 10 + 1);  // 1-10 cycle delay
    valid <= 1;
end

initial begin
    #1000;
    $finish;     // End simulation completely
    // Or
    $stop;       // Pause simulation (can resume in some tools)
    // Exit with status code
    $finish(0);  // 0 = success, 1 = warning, 2 = error
end
// Waveform dumping (VCD format)
initial begin
    $dumpfile("waves.vcd");
    $dumpvars(0, top_tb);  // Dump all signals in top_tb
    $dumpvars(1, top_tb);  // Dump only top level
    $dumpvars(0, top_tb.u_dut.u_alu);  // Specific hierarchy
end