Behavioral Modeling

module fsm (
    input  wire clk, rst_n, start,
    output reg  done, busy
);
    localparam IDLE = 2'b00, RUN = 2'b01, DONE = 2'b10;
    reg [1:0] state, next_state;
    // Sequential: state register
    always @(posedge clk or negedge rst_n)
        if (!rst_n) state <= IDLE;
        else state <= next_state;
    // Combinational: next state
    always @(*) begin
        next_state = state;
        case (state)
            IDLE: if (start) next_state = RUN;
            RUN:  next_state = DONE;
            DONE: next_state = IDLE;
        endcase
    end
    // Output logic
    always @(posedge clk or negedge rst_n)
        if (!rst_n) begin done <= 0; busy <= 0; end
        else begin
            done <= (state == DONE);
            busy <= (state == RUN);
        end
endmodule