In-Order vs Out-of-Order Execution

Understanding transaction ordering is critical for verifying complex pipelined bus protocols like AXI, PCIe, and OCP.

Architecture: Latency vs. Throughput

In the world of high-performance silicon, Ordering defines the CPU or Interconnect's ability to handle operations. While In-Order execution is simpler to verify, Out-of-Order (OoO) execution is the backbone of modern SoC throughput.

The Trade-off:

In-Order: Predictable, low area. But a single slow memory read stalls the entire pipeline (Head-of-Line Blocking).
Out-of-Order: Complex, high area. Allows the silicon to "jump over" stalled instructions to find independent work, maximizing functional unit utilization.

The Data Dependency Challenge

The core difficulty in verifying OoO logic is Dependency Tracking. If Transaction B depends on the result of Transaction A, the hardware must ensure they are retired (committed) in the correct logical order, even if they were executed out-of-order.

Verification Strategy:

To verify this, your testbench must model a Scoreboard with Dependency Checks. You don't just check if the data is correct; you check if the sequence of side effects (like memory writes) matches the architectural intent.

Validating Reorder Buffers (ROB)

Modern designs use a Reorder Buffer (ROB) to manage the transition from OoO execution back to In-Order retirement. This is a primary target for verification bugs.

Scoreboard: Hazard Check


function void check_hazard(axi_item new_tr);
    foreach (pending_tr[i]) begin
        // RAW Hazard: Read-After-Write
        if (new_tr.is_read && pending_tr[i].is_write && 
           (new_tr.addr == pending_tr[i].addr)) begin
            `uvm_info("HAZARD", "Tracking dependency for address match", UVM_HIGH)
            // Logic to ensure tr[i] completes before new_tr
        end
    end
endfunction

Summary of Ordering Rules

Feature	Strong Ordering (In-Order)	Weak Ordering (OoO)
Throughput	Limited by slowest op	Optimized (No stalls)
Bus Protocols	APB, AHB (Simple)	AXI, CHI, ACE
Scoreboard Key	FIFO Queue	Assoc Array + ID
Verification Focus	Timing / Handshake	Deadlocks / Hazards

Previous Out-of-Order Scoreboarding Next Scalable Architecture & Parameterization