One of the most frustrating issues in UVM verification is the "Silent Hang."
The simulation doesn't crash, no error is reported, but the clock keeps ticking until
the global timeout (e.g., $finish at 1ms) kills it.
Why does this happen?
Usually, a component (like a Driver or Scoreboard) raised an objection but
never dropped it. Because UVM waits for all objections to drop before ending the phase,
the simulation runs forever.