What Does a Monitor Do?
The Simple Version: The Monitor is your testbench's "eyes and ears." It watches what's happening on your design's signals and reports it to other components.
Think of it like: A security camera. It passively observes and records everything without interfering with what's happening.
A UVM Monitor is the "Eyes and Ears" of your verification environment. Its primary job is to extract pin-level activity from the DUT and reconstruct it into high-level transaction objects. Crucially, a monitor is Passiveยit must never drive or modify interface signals.
Key Characteristics:
- Non-Intrusive: Samples signals without affecting simulation state.
- Analysis Port (AP): Broadcasts reconstructed items to subscribers (Scoreboards, Coverage).
- Shared Resource: Can be used by multiple testbench components simultaneously.