In simple protocols like APB, transactions appear on the bus in the
exact order they were requested. Verifying this is easy: you use a
uvm_tlm_analysis_fifo and compare items as they arrive.
However, advanced SoC protocols like AXI or PCIe support Out-of-Order (OoO) completions. A read request with ID=5 might finish after a read request with ID=10 because of interconnect latency or memory controller arbitration.
The FIFO Trap:
If you use a standard FIFO queue for an OoO protocol, the first transaction that returns out of sequence will trigger a mismatch error, even though the data might be perfectly correct. You need a Searchable Buffer instead.