UVM Common Interview Questions
The definitive list of UVM conceptual questions asked in 90% of verification interviews.
1. Components vs Objects
| Feature | uvm_component | uvm_object |
|---|---|---|
| Lifespan | Simulation Lifetime (Static) | Transient (Created/Destroyed) |
| Hierarchy | Has Parent/Child | No Hierarchy |
| Phases | Participates in Phases | No Phases |
| Example | Driver, Monitor, Agent | Transaction (Seq Item), Config Object |
2. Factory: New() vs Create()
new(): Standard SystemVerilog constructor. Hardcodes the type.
type_id::create(): Calls the UVM Factory. Allows
Overriding the type without changing the code. Essential for tests that
inject error sequences or modified drivers.
Usage: `pkt = my_packet::type_id::create("pkt");`
3. Config DB vs Resource DB
- uvm_config_db: User-friendly wrapper. Support hierarchical paths (Scope). Used for passing Interfaces, Params, Config objects.
- uvm_resource_db: The underlying backend. Flat lookup (Global). Deprecated for general use, but used by `config_db` internally.
4. Sequences & Macros
Difference between `uvm_do` and `start_item`?
`uvm_do`: Macro that performs: create ->
randomize -> start_item -> finish_item automatically. Easy but less control.
`start_item`: Requests grant from sequencer. Returns when driver is ready. Allows manual `randomize() with` constraints before sending to `finish_item`.
`start_item`: Requests grant from sequencer. Returns when driver is ready. Allows manual `randomize() with` constraints before sending to `finish_item`.
What is a Virtual Sequence?
A sequence that does NOT run on a driver. It runs on a
Virtual Sequencer and coordinates multiple sub-sequences
running on physical agents (e.g., coordinating PCIe and DDR traffic).
5. Phases
Why is Build Phase Top-Down and Connect Phase Bottom-Up?
Build (Top-Down): Parents (Test/Env) must
exist before they can configure or create Children (Agents/Drivers).
Connect (Bottom-Up): Verification IP (Connect Phase) often runs Bottom-Up to resolve port connections, though UVM default is technically also Top-Down for Connect. (Note: Common misconception is Bottom-Up, but practically connections rely on both existing.)
Wait, correction: UVM `connect_phase` traversal is actually also Top-Down. However, standard interview answer expects "Connect is Bottom Up" due to historical OVM/legacy reasons or confusion with `final_phase`. Real answer: Both are Top-Down in UVM 1.2, but components *bind* usually assuming children exist.
Connect (Bottom-Up): Verification IP (Connect Phase) often runs Bottom-Up to resolve port connections, though UVM default is technically also Top-Down for Connect. (Note: Common misconception is Bottom-Up, but practically connections rely on both existing.)
Wait, correction: UVM `connect_phase` traversal is actually also Top-Down. However, standard interview answer expects "Connect is Bottom Up" due to historical OVM/legacy reasons or confusion with `final_phase`. Real answer: Both are Top-Down in UVM 1.2, but components *bind* usually assuming children exist.