AHB Functional Coverage Plan

A comprehensive list of coverpoints and crosses required to verify an AHB Master or Slave VIP.

Basic Signal Coverage

Verify that all valid values of control signals have been observed.

HTRANS: IDLE, BUSY, NONSEQ, SEQ.
HBURST: SINGLE, INCR, WRAP4, INCR4, WRAP8, INCR8, WRAP16, INCR16.
HCLK / HRESETn: Reset during active transactions.
HRESP: OKAY, ERROR (Retry/Split if applicable).
HSIZE: 8-bit, 16-bit, 32-bit, up to maximum bus width.
HWRITE: Read and Write transactions.

Critical Cross Coverage

SystemVerilog snippet


covergroup ahb_cg @(posedge hclk);
  cp_trans: coverpoint htrans {
    bins active[] = {NONSEQ, SEQ};
    bins idle   = {IDLE};
    bins busy   = {BUSY};
  }
  cp_burst: coverpoint hburst;
  cp_size:  coverpoint hsize;
  cp_write: coverpoint hwrite;
  cp_resp:  coverpoint hresp;
  // Cross: Burst Types vs Transfer Sizes
  cx_burst_size: cross cp_burst, cp_size;
  // Cross: Read/Write vs Burst Types
  cx_rw_burst: cross cp_write, cp_burst;
  // Cross: Response vs Transfer Type (Error on SEQ etc.)
  cx_resp_trans: cross cp_resp, cp_trans;
endgroup

Corner Cases to Cover

Back-to-Back Bursts: NONSEQ immediately following the last SEQ of previous burst.
Busy Cycles: Inserting BUSY cycles in the middle of a burst.
HREADY Stalling: Slave holding HREADY low for maximum allowed cycles.
Early Termination: Master terminating an undefined length burst (INCR).
Address Boundaries: WRAP bursts hitting the 1KB boundary condition.

Previous SVA for AHB Verification