AHB Pipelining

The core feature of AHB is its pipelined nature, allowing Address and Data phases to overlap for higher performance.

Address vs Data Phase

⚡ Key Concept

Address Phase (A): Master drives HADDR and Control signals. Lasts 1 cycle (usually).
Data Phase (D): Slave drives HRDATA (or Master drives HWDATA). Can be extended by HREADY.
Overlap: The Data Phase of Transfer N happens simultaneously with the Address Phase of Transfer N+1.

Unlike APB, where setup and access happen sequentially for one transfer before the next begins, AHB pipelines them. This means the bus is fully utilized; in every clock cycle, an address is being presented and data is being transferred (for the previous address).

Pipeline Visualization

Pipeline Mechanics:

Cycle T1: Address A1 is valid (Address Phase).
Cycle T2: Data D1 is valid (Data Phase). Simultaneously, Address A2 is valid.
Efficiency: The bus carries both Address and Data payload in every cycle, maximizing throughput.

Notice how ADDR2 appears on the bus while DATA1 is being transferred. This overlap doubles the theoretical bandwidth compared to a non-pipelined bus.

Impact of Wait States

If a slave deasserts HREADY (Low) during the Data Phase of Transfer 1, the Address Phase of Transfer 2 is frozen/extended. The Master must hold ADDR2 stable until `DATA1` completes.

Why?

Because the bus signals (HADDR, HTRANS) can only change when HREADY is HIGH. If the previous data phase is stuck, the pipeline stalls.

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