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HRESP Error Response

Unlike APB which has a simple error bit, AHB uses a complex 2-cycle error response mechanism. Verification engineers must master this.

The 2-Cycle Error Rule

When an AHB Slave decides to error out (e.g., writing to Read-Only memory, or accessing unmapped address), it signals HRESP = ERROR (1).

The Protocol Requirement

An ERROR response requires TWO CYCLES to complete:

  1. Cycle 1 (Phase 1): Slave asserts HRESP = ERROR and drives HREADY = 0 (EXTEND). This halts the pipeline and warns the Master.
  2. Cycle 2 (Phase 2): Slave keeps HRESP = ERROR and drives HREADY = 1. This terminates the transfer.

Waveform Analysis

  • Time 'a': Slave detects error. Drives HRESP=1, HREADY=0. Master sees "wait, something is wrong".
  • Time 'b': Slave drives HRESP=1, HREADY=1. Master samples Error. Bus returns to IDLE.

Why 2 Cycles?

AHB is pipelined. The Address Phase of the next transfer might be happening while the Data Phase of the current transfer errors out.

The first cycle (HREADY=0) gives the Master time to cancel the pending Address Phase logic and prepare to handle the abort/exception. If it were a single cycle, the Master might not have enough timing margin to stop the pipeline gracefully.

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