HCLK
|
Clock Source | Bus clock. All signal timings are related to the rising edge of HCLK. |
HRESETn
|
Reset Controller | Active LOW bus reset. Forces all bus modules to a known initialization state. |
AHB Signals Reference
A comprehensive guide to every signal in the AMBA AHB protocol, grouped by function. Understanding these signals is the first step to mastering bus verification.
HTRANS Encoding at a Glance
| Type | Code | Meaning |
|---|---|---|
IDLE |
00 |
No transfer requested |
BUSY |
01 |
Wait state within burst |
NONSEQ |
10 |
First transfer of burst |
SEQ |
11 |
Remaining burst transfers |
Global Signals
Master Signals (Address Phase)
These signals are driven by the Master to initiate a transfer.
HADDR
|
32 | System address bus. |
HTRANS
|
2 |
Transfer type. 00: IDLE (No transfer) 01: BUSY (Valid burst cycle, but Master not ready) 10: NONSEQ (First transfer of burst or single) 11: SEQ (Next transfer of burst) |
HWRITE
|
1 | HIGH for Write, LOW for Read. |
HSIZE
|
3 | Transfer size (000=8bit, 001=16bit, 010=32bit...). |
HBURST
|
3 | Burst type (SINGLE, INCR4, WRAP8, etc.). |
HPROT
|
4 | Protection. [0]: Op/Data, [1]: User/Priv, [2]: Bufferable, [3]: Cacheable. |
Slave Signals (Response Phase)
These signals are driven by the Slave to respond to the Master.
HREADY
|
1 |
Transfer Done. HIGH: Signal transfer finished. LOW: Slave is extending the transfer (wait state). |
HRESP
|
2 |
Transfer Status. 00: OKAY 01: ERROR 10: RETRY (Protocol v2.0 only) 11: SPLIT (Protocol v2.0 only) |
HRDATA
|
32/64 | Read Data bus. Source is Slave, sink is Master. |
Data Signals
HWDATA
|
Master | Write Data bus. Valid only during write transfers (HWRITE=1). |
Common Interview Questions
Q: What happens if HREADY is low during the address phase?
Trick question! The AHB protocol is pipelined. If
HREADY is low, it means
the previous data phase is stuck. The current address phase cannot complete, so
the Master must hold HADDR, HTRANS, etc. stable until
HREADY goes high.
Q: Can HTRANS change from IDLE to NONSEQ if HREADY is low?
No. Master signals must remain stable when HREADY is low, with the exception of leaving
IDLE state in some specific limited cases (HTRANS can transition from IDLE to NONSEQ,
but the address must then be held). However, general rule of thumb: Wait for HREADY.