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Basic Read & Write Transfers

The simplest AHB transfer consists of an Address Phase and a Data Phase. Even without bursts or pipelining, understanding this fundamental unit is key.

The Two Phases

Every AHB transfer requires at least two clock cycles to complete:

  1. Address Phase (Cycle N): The Master drives address and control signals (HADDR, HWRITE, HTRANS).
  2. Data Phase (Cycle N+1): The data is sampled (HWDATA) or driven (HRDATA).

Important

Because of pipelining, the Data Phase of Transfer A happens at the same time as the Address Phase of Transfer B.

Simple Write Transfer

A zero-wait-state write.

  • T0: Address A is driven.
  • T1: Address B is driven. Simultaneously, Data A is transferred.
  • T2: Data B is transferred. The pipeline is fully active.
  • Pipeline: Notice Address B (Next Transfer) starts during Data A.

    • Simple Read Transfer

    A zero-wait-state read.

    { signal: [ { name: "HCLK", wave: "p..." }, { name: "HADDR", wave: "22..", data: ["A", "B"] }, { name: "HTRANS", wave: "22..", data: ["NSEQ", "IDLE"] }, { name: "HWRITE", wave: "0..." }, { name: "HRDATA", wave: "x4..", data: ["D(A)"] }, { name: "HREADY", wave: "1..." } ], head: { text: "AHB Pipelined Read" }, edge: ['a~>b Addr A', 'b~>c Data A', 'c~>d Data B'] }
  • Pipeline Read: Similar to write, Data A returns while Address B is being issued.
  • T2: Data B returns.

    • Wait States (HREADY)

    If the Slave needs more time (e.g., memory access latency), it pulls HREADY LOW during the Data Phase. The Master must extend the Data Phase until HREADY goes HIGH.

    { signal: [ { name: "HCLK", wave: "p...." }, { name: "HADDR", wave: "23.4.", data: ["A", "B", "C"] }, { name: "HTRANS", wave: "22.2.", data: ["NSEQ", "NSEQ", "IDLE"] }, { name: "HWRITE", wave: "1...." }, { name: "HWDATA", wave: "x.45.", data: ["D(A)", "D(B)"] }, { name: "HREADY", wave: "10.1." } ], head: { text: "AHB Wait State (HREADY Low)" }, edge: ['c-d Wait State', 'd~>e Ready'] }
    Wait State Logic:
    • T1: Slave pulls HREADY LOW. Data Phase A cannot complete.
    • T2: Master MUST hold Address B and Control B stable (Extension).
    • T3: HREADY goes HIGH. Data A is sampled, and Address B is accepted.

    Common Interview Questions

    Q: Who drives the HREADY signal?
    The Slave drives HREADYOUT to indicate it is ready. The Mux/Arbiter combines all slave ready signals into a system-wide HREADY which is fed back to the Master and all Slaves.
    Q: When is HWDATA valid?
    HWDATA is valid during the Data Phase (one cycle after the Address Phase). It must be stable until HREADY is HIGH at the rising edge of HCLK.
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