Write Transfers

How data is written to a peripheral using the Setup and Access phases.

Basic Write (No Wait States)

A write transfer completes in 2 clock cycles if the Slave is ready immediately.

Step-by-Step Analysis:

T1 (Setup): Master drives Address, Data, and asserts PSEL. PENABLE remains LOW.
T2 (Access): Master asserts PENABLE. Slave must be ready.
T3 (Sample): At the rising edge, PREADY is HIGH, so the slave captures the data and the transfer completes.

Write with Wait States

If PREADY is LOW during the Access phase, the Master must hold all signals stable until PREADY goes HIGH.

{ signal: [ { name: "PCLK", wave: "p....", node: '.a.b.c.d' }, { name: "PSEL", wave: "01..0", node: '.e....' }, { name: "PENABLE", wave: "0.1.0", node: '...f..' }, { name: "PWRITE", wave: "01..0" }, { name: "PADDR", wave: "x3..x", data: "Addr" }, { name: "PWDATA", wave: "x4..x", data: "Data", node: '.......g' }, { name: "PREADY", wave: "1.01." } ], head: { text: "APB Write with Wait State", tick: 0 }, edge: ['a~>e Setup', 'b~>f Access', 'c-g Wait', 'd-|>g Sample'] }

Handling Wait States:

T2 (Access): PREADY is LOW. The slave is busy.
T3 (Wait): Master must hold PSEL, PENABLE, and signals stable.
T4 (Done): PREADY goes HIGH. Data is successfully sampled at the rising edge.

SVA Check for Write Stability

Ensuring data doesn't change during wait states.

property p_write_stable;
    @(posedge pclk) disable iff (!presetn)
    (psel && penable && !pready && pwrite) |-> 
    ($stable(pwdata) && $stable(paddr) && $stable(pwrite));
endproperty
assert property(p_write_stable);

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