APB Error Responses (PSLVERR)

Understanding how the APB slave signals an error condition using the PSLVERR signal, and how it impacts the transfer timing.

The PSLVERR Signal

⚡ TL;DR

PSLVERR: Indicates a transfer failure (Read or Write).
Timing: Must be valid when PSEL, PENABLE, and PREADY are all HIGH.
Optional: If a slave doesn't support errors, this pin is tied LOW.

In APB (Advanced Peripheral Bus), transfers are usually assumed to succeed. However, a slave may encounter an error (e.g., writing to a Read-Only register, or accessing an unmapped address). The PSLVERR (Peripheral Slave Error) signal is used to report this.

Error Transaction Timing

Usually, a transfer completes in the ACCESS phase when PREADY goes HIGH. If PSLVERR is also asserted HIGH during this cycle, the transfer is considered failed.

Important Rule

For a Write Error, the data in the register is not guaranteed to be updated (or not updated). For a Read Error, the data on PRDATA is invalid.

Timing Diagram (Concept)


      Setup Phase      Access Phase
          |                |
PCLK      ^                ^                ^
          |                |                |
PSEL      |________________|________________|____
          |                |                |
PENABLE   ________|_________________|________
          |                |                |
PREADY    __________________________|________
          |                |                |
PSLVERR   __________________________|________
          |                |     HIGH       |
                            (Error Sampled Here)

Interview Questions

Can PSLVERR generally occur in the Setup Phase?

No. PSLVERR is only sampled in the ACCESS phase when PENABLE and PREADY are HIGH. Asserting it earlier has no effect on the protocol compliance, but it signals the status of the CURRENT transfer.

Previous Read Transfers