Read Transfers

Reading data from a peripheral is identical to writing, but the direction of data is reversed.

Basic Read Timing

The Master drives Address and Control (PWRITE=0). The Slave drives PRDATA when PREADY is High.

Read Cycle Analysis:

T1 (Setup): Master sets PWRITE=0 and drives Address.
T2 (Access): Master asserts PENABLE. Slave prepares data.
T3 (Sample): PREADY must be HIGH. Master samples PRDATA at the rising edge.

SVA Check for Read Data

If PREADY is low, the Slave CAN change PRDATA (unlike the Master which must hold PWDATA stable). However, the PRDATA is only valid when PREADY is HIGH.

// Ensure Unknown ('X') is not propagated on valid read
property p_valid_read_data;
    @(posedge pclk) disable iff (!presetn)
    (psel && penable && pready && !pwrite) |-> !$isunknown(prdata);
endproperty
assert property(p_valid_read_data);

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