APB Operating States

State      | PSEL | PENABLE
-----------------------------IDLE       |  0   |   0     // No transfer
SETUP      |  1   |   0     // First Cycle (Address Phase)
ACCESS     |  1   |   1     // Second Cycle (Data Phase)
Transitions:
1. IDLE   -> SETUP  : When transfer Required.
2. SETUP  -> ACCESS : Always happens on next clock edge.
3. ACCESS -> ACCESS : If PREADY == 0 (Wait State).
4. ACCESS -> IDLE   : If PREADY == 1 and No More Transfers.
5. ACCESS -> SETUP  : If PREADY == 1 and Next Transfer Pending.

module apb_master_fsm (
    input logic pclk, presetn,
    input logic transfer_req,
    input logic pready,
    output logic psel, penable,
    output logic [1:0] state_out
);
    typedef enum logic [1:0] {
        IDLE   = 2'b00,
        SETUP  = 2'b01,
        ACCESS = 2'b10
    } state_t;
    state_t state, next_state;
    // Sequential Logic
    always_ff @(posedge pclk or negedge presetn) begin
        if (!presetn) state <= IDLE;
        else          state <= next_state;
    end
    // Combinational Next State Logic
    always_comb begin
        next_state = state;
        case (state)
            IDLE: begin
                if (transfer_req) next_state = SETUP;
            end
            SETUP: begin
                // Unconditionally go to ACCESS
                next_state = ACCESS;
            end
            ACCESS: begin
                if (pready) begin
                    if (transfer_req) next_state = SETUP;  // Back-to-back
                    else              next_state = IDLE;
                end
                // Else stay in ACCESS (Wait State)
            end
        endcase
    end
    // Output Logic
    assign psel    = (state == SETUP) || (state == ACCESS);
    assign penable = (state == ACCESS);
    assign state_out = state;
endmodule