Static Timing Analysis (STA)

What is it?

Static Timing Analysis (STA) is a method of computing the expected timing of a digital circuit without requiring simulation. It breaks the design into timing paths (Register-to-Register, Input-to-Register, Register-to-Output) and calculates the sum of delay delays along these paths.

Why is it needed?

Dynamic simulation (verifying logic with waveforms) is too slow to cover all corners and all paths. STA exhaustively checks every single path in the design against timing constraints to guarantee operations at frequency (e.g., 1GHz) under worst-case voltage and temperature (PVT) conditions.

Definition: The minimum amount of time the data must be stable at the input of the capture Flip-Flop before the clock edge arrives.

Violation Consequence: If data arrives too late, the flop samples old data or goes metastable. The chip fails to run at the target speed.

Data Arrival Time   = T_launch_clk + T_clk_q + T_comb_delay
Data Required Time  = T_capture_clk + T_period - T_setup
Setup Slack = Data Required - Data Arrival
            = (T_period - T_setup) - (T_clk_q + T_comb + T_skew)

How to Fix Setup Violations:

• Reduce `T_comb`: Optimize combinational logic, use faster gates (LVT cells).
• Reduce `T_period`: Slow down the clock frequency (last resort).
• Useful Skew: Deliberately delay the capture clock (risky for Hold).

Definition: The minimum amount of time the data must remain stable after the clock edge.

Violation Consequence: If data changes too fast, the "new" data overwrites the "current" data before it is safely latched. This is a functional failure independent of clock speed.

Data Arrival Time   = T_launch_clk + T_clk_q + T_comb_delay
Data Required Time  = T_capture_clk + T_hold
Hold Slack = Data Arrival - Data Required
           = (T_clk_q + T_comb) - (T_hold + T_skew)

How to Fix Hold Violations:

• Increase `T_comb`: Insert buffers/delay cells into the fast path.
• Reduce Clock Skew: Balance the clock tree.
• Note: You cannot fix Hold by slowing down the clock. It must be fixed during P&R.

Exceptions tell the STA tool to ignore specific paths or relax constraints.

• False Path: A path that functionally cannot be sensitised (e.g., Configuration Registers that are static during operation, or Mux paths that are mutually exclusive). `set_false_path -from [get_ports RST]`.
• Multi-Cycle Path: Paths designed to take more than 1 cycle. Example: A complex multiplier allowed to take 2 cycles. We tell STA: "Check setup at edge 2, not edge 1."