FSM Design Guidelines

Finite State Machines (FSMs) are the brains of control logic. They dictate sequence: Idle -> Request -> Grant -> Data -> Idle.

Moore Machine

• Output depends on: Current State ONLY.
• Pros: Output is synchronous to state. Less sensitive to input glitches once state is captured. Usually cleaner timing paths.
• Cons: Response is delayed by 1 cycle (Input change -> Next Clock -> State Change -> Output Change).

Mealy Machine

• Output depends on: Current State AND Current Input.
• Pros: Immediate response (Input change -> Output change in same cycle). Uses fewer states.
• Cons: Combinational path from Input to Output. Glitches on input propagate directly to output.

• Binary Encoding (00, 01, 10, 11):
  Pros: Minimal Flip-Flops (N states = log2(N) flops).
  Cons: High combinational decoding logic. More power consumption due to multiple bits toggling.
• One-Hot Encoding (0001, 0010, 0100, 1000):
  Pros: Fast modification logic (just 2 bits change). Easy to debug (Bit N = State N). Fast Fmax.
  Cons: Uses N Flip-Flops for N states. (Not an issue for modern FPGAs).
• Gray Encoding (00, 01, 11, 10):
  Pros: Only 1 bit changes per transition. Minimizes power and glitches.
  Cons: Harder to design next-state logic manually.

Separating the logic into three blocks is the industry standard for clarity and flexibility.

// 1. Sequential Block: State Register
always @(posedge clk or negedge rst_n) begin
    if (!rst_n)      current_state <= IDLE;
    else             current_state <= next_state;
end
// 2. Combinational Block: Next State Logic
always @(*) begin
    // Default assignment prevents latches
    next_state = current_state; 
    case (current_state)
        IDLE: if (start) next_state = RUN;
        RUN:  if (done)  next_state = IDLE;
        default:         next_state = IDLE; // Safety
    endcase
end
// 3. Registered Output Block (Moore-like, Glitch Free)
always @(posedge clk or negedge rst_n) begin
    if (!rst_n) out_valid <= 1'b0;
    else begin
        // Look ahead at next_state for Moore to react fast, 
        // OR depend on current_state for standard Moore
        out_valid <= (next_state == RUN); 
    end
end