Digital Primitives & Coding

The building blocks of RTL. Understanding how Verilog maps to hardware Gates.

1. Latch vs Flip-Flop

Latch: Level-sensitive. Transparent when Enable is High. (Comb Loop risk!).
Flip-Flop: Edge-sensitive. Samples only on clock edge. (Safe).

Unwanted Latches: Only happen in Combinational (`always @*`) blocks if you miss a condition.
Example: `if (a) y = 1;` (Implies: if !a, keep old y -> LATCH).
Fix: `if (a) y = 1; else y = 0;`

2. Multiplexer (Mux)

The universal logic gate. Can implement any boolean function.

4:1 Mux using Case

always @(*) begin
    case (sel)
        2'b00: y = a;
        2'b01: y = b;
        2'b10: y = c;
        2'b11: y = d;
        default: y = 0; // Good practice
    endcase
end