Low Power Design Basics
Understanding UPF concepts: How to verify chips that turn off sections to save battery.
1. Clock Gating (Dynamic Power)
Concept: Stop the clock toggling for idle modules. Saves switching power (P = CV²f).
Implementation: Integrated Clock Gating (ICG) cells.
AND Gate + Latch (to prevent glitches).
Verilog: Automatic insertion by Synthesis tools.
2. Power Gating (Leakage Power)
Concept: Cut off VDD supply to a block entirely. Saves leakage current.
Risk: When block wakes up, all internal states are LOST (X). Outputs
become floating (Z).
3. Special Cells (UPF)
- Isolation Cell (ISO): Placed at outputs of a Power Gated domain. Clamps output to '0' or '1' so the 'Z' doesn't propagate to active logic.
- Retention Register (SRPG): Special Flip-Flop with a shadow latch powered by "Always On" supply. Saves state before power down; restores on wake up.
- Level Shifter (LS): Converts voltage levels (e.g., 0.8V signal to 1.2V domain). prevents crowbar current.