Verilog Timing & Delays
Setup/Hold times, Inertial vs Transport delays.
Intermediate Level
Define Setup and Hold Time.
Setup: Time data must be stable BEFORE the clock edge.
Hold: Time data must be stable AFTER the clock edge.
Difference between Inertial Delay and Transport Delay?
Inertial (Default): Glitches shorter than delay are filtered out. (Models logic gates).
Transport: All pulses are propagated, just delayed. (Models wires).
Advanced Level
Synthesizable Delay?
Delays (`#10`) are NOT synthesizable. Hardware cannot just "pause". You must use Counters or Shift Registers to create timing delays in RTL.