Verilog Basic Concepts

Questions on Verilog Data Types, Reg vs Wire, and basic syntax.

Beginner Level

What is the difference between `reg` and `wire`?

wire: Represents a physical connection. Driven by continuous assignment (`assign`) or output of a module. Cannot store a value.

reg: Represents a storage element (variable). Assigned inside procedural blocks (`always`, `initial`). May or may not synthesize to a flip-flop.

What is the `tri` net type?

Used for tri-state logic (0, 1, Z). If multiple drivers drive it, it supports the High-Z state effectively, often used in bidirectional pads.

How do you represent a negative number in Verilog?

Verilog uses 2's Complement format. A signed 4-bit number ranges from -8 to +7. You can declare signals as `signed` (e.g. `reg signed [3:0] a;`).

What is the default value of a `reg` and `wire` at start of simulation?

reg: `x` (Unknown).

wire: `z` (High Impedance).

What is the result of `4'b1001 + 4'b0111`?

`4'b1001` (9) + `4'b0111` (7) = 16. In 4-bit arithmetic, this overflows to `0000`. The carry is lost unless stored in a 5-bit result.