Verilog Synthesis Issues
Synthesis vs Simulation mismatches, sensitivity lists, and race conditions.
Intermediate Level
The list of signals in `always @(...)`. If you miss a signal that is read in the block, Simulation will behave as a latch (holding value until other signals change), but Synthesis will behave as combinational logic (ignoring the list). Result: Synthesized hardware does not match Simulation.
No. `initial` blocks are for simulation initialization only. They are ignored by synthesis tools (except sometimes for FPGA ROM initialization).
Advanced Level (Tricky)
It tells the synthesizer to treat the case statement as if all conditions are mutually exclusive, building a Mux instead of a Priority Encoder. Dangerous if cases overlap in reality.
For 1-bit signal: Use a 2-Flip-Flop Synchronizer.
For Multi-bit bus: Use a FIFO (Gray code pointers) or a Handshake protocol. Never just synchronize individual bits of a bus separately.