Verilog Operators
Logical, Bitwise, Reduction, and Conditional operators.
Beginner Level
Difference between `==` and `===`? (Tricky)
`==` (Logical Equality): Returns X if any operand contains X or Z.
`===` (Case Equality): Compares X and Z as literal values. Returns 0 or 1 always. Not synthesizable.
What is the Reduction Operator? Example?
It accepts a vector and returns a single bit. `&a` (ANDs all bits of a), `|a` (ORs all bits). Useful for parity checks or checking if 'All Ones'.
Intermediate Level
Difference between `>>` and `>>>`?
`>>` (Logical Shift): Shifts right, fills with 0.
`>>>` (Arithmetic Shift): Shifts right, fills with Sign Bit (if declared signed). Important for signed math.