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Ordering and Transaction IDs

AXI supports Out-of-Order transaction completion, allowing high-performance slaves to return data as soon as it is available, rather than in the order requested.

Transaction IDs

Transactions are tagged with an ID (AWID for writes, ARID for reads).

  • Same ID Rule: Transactions with the SAME ID must be completed In Order.
  • Different ID Rule: Transactions with DIFFERENT IDs can be completed Out of Order.
Analysis:
  • Issue Order: Master requests A (ID0) then B (ID1).
  • Return Order: Slave returns B (ID1) before A (ID0).
  • Validity: Since IDs are different, this is legal and efficiently uses bandwidth.

Data Interleaving

Read Interleaving: Data beats from different Read transactions (different IDs) can be interleaved on the Read Data Channel. The Master uses RID to reassemble the messages.

Write Interleaving: Deprecated in AXI4. In AXI4, write data must be sent in the same order as the write addresses for the same ID. Most implementations enforce order for all writes to simplify design.

Verification Strategy: OoO Scoreboarding

Verifying Out-of-Order (OoO) completion is a common task in high-end DV roles. A simple FIFO-based scoreboard will fail because the Slave can return data in any order for different IDs.

The Solution: Associative Arrays (Maps)

To verify OoO transactions in UVM:
  1. Store expected transactions in an associative array indexed by ID: expected_q[axi_id].
  2. Since multiple transactions can have the same ID (but must be in order), use a queue for each ID entry: transaction expected_q[int][$].
  3. When a response comes back, look up the queue for that RID, pop the front, and compare.

Common Bug: Interconnect incorrectly "tags" a transaction with the wrong ID, causing data to be delivered to the wrong Master. This is caught by ensuring every Master only sees transactions with its own assigned ID range.

Common Interview Questions

Q: Why use different IDs?
To prevent head-of-line blocking. A slow peripheral/memory shouldn't block access to a fast on-chip SRAM. Using different IDs allows the interconnect to juggle responses based on availability.
Q: What is AXI ID width?
It is implementation dependent (usually 4 to 12 bits). The interconnect appends bits to the Master's ID to identify which Master sent the request, so the Slave sees a wider ID than the Master sent.
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