Atomic Transactions (Exclusive Access)

How multi-core processors synchronize using AXI Exclusive Access monitoring.

Why Atomic Transactions?

In a multi-master system (like a dual-core CPU), two masters might try to update the same memory location (e.g., a Semaphore or Spin-lock) at the same time. Without atomicity, you get a "Read-Modify-Write" race condition.

The Race Condition Scenario

  • Master A reads Address 0x100 (Value = 0).
  • Master B reads Address 0x100 (Value = 0) before A writes back.
  • Master A writes 1 to 0x100.
  • Master B writes 1 to 0x100.
  • Result: Both think they acquired the lock, but only one should have!

The Exclusive Access Mechanism

AXI uses the ARLOCK and AWLOCK signals alongside an Exclusive Monitor in the slave/interconnect to solve this.

Step-by-Step Flow

  1. Exclusive Read: Master A sends a Read with ARLOCK=1 (Exclusive).
  2. Monitor Setup: The Slave (or Interconnect) records Master A's ID and the Address in an "Exclusive Monitor" table.
  3. Exclusive Write: Master A sends a Write with AWLOCK=1 and the same ID/Address.
  4. Validation: The Slave checks the Monitor:
    • If No other Master has written to that address since step 1, the Write SUCCEEDS. Response = EXOKAY.
    • If Another Master (Master B) wrote to that address in between, the Monitor entry is cleared. Master A's Write FAILS. Response = OKAY (not EXOKAY).
ARM Assembly Equivalent

loop:
    LDREX R1, [Lock_Addr]   ; Exclusive Read
    CMP R1, #0              ; Is it free?
    BNE loop                ; If locked, retry
    MOV R1, #1
    STREX R2, R1, [Lock_Addr] ; Exclusive Write (Try to lock)
    CMP R2, #0              ; Did STREX succeed? (0=Success, 1=Fail)
    BNE loop                ; If failed (someone else stole it), retry
                            

Verification Corner Cases

Verifying the Exclusive Monitor is one of the trickiest parts of AXI verification.

Scenario Expected behavior
Pass Case Excl Read -> (No interference) -> Excl Write. Result: EXOKAY.
Fail Case (Collision) Excl Read (A) -> Normal Write (B) -> Excl Write (A). Result: OKAY (Fail). Data is NOT updated.
Reset Case Excl Read (A) -> Reset -> Excl Write (A). Result: OKAY (Fail). Monitor must clear on reset.
Different ID Excl Read (ID=1) -> Excl Write (ID=2). Result: OKAY (Fail). Must match ID.

Locked Transactions (Legacy)

AXI3 supported "Locked" transactions (locking the entire bus). AXI4 removed this because it kills bandwidth. Only Exclusive Access (Address-based locking) is supported in AXI4.