| Feature | AXI (Advanced eXtensible Interface) | AHB (Advanced High-performance Bus) | APB (Advanced Peripheral Bus) |
|---|---|---|---|
| Primary Use Case | High-BW, Low-Latency (CPU, DDR, GPU) | Medium-BW, System Control (DMA, Internal RAM) | Low-BW, Control Registers (UART, Timer, GPIO) |
| Architecture | 5 Independent Channels (Parallel) | Pipelined (Address phase, then Data phase) | Simple State Machine (Setup, Access) |
| Handshake | Ready/Valid (Both Reference Clock) | HREADY (Slave controls flow) | PENABLE / PREADY |
| Out-of-Order? | Yes (ID based) | No (Strictly Ordered) | No |
| Multiple Outstanding? | Yes | Limited (Pipelined only) | No |
| Full Duplex? | Yes (Read/Write simultaneous) | No (Shared Bus) | No |
AMBA Protocols: AXI vs AHB vs APB
Understanding when to use which protocol is the hallmark of a system architect. While AXI dominates high-performance blocks, AHB and APB still play critical roles in modern SoCs. Here's a breakdown from a verification perspective.
The "Cheat Sheet" Comparison
Verification Complexity & Common Bugs
AXI Verification Challenges
AXI is the hardest to verify due to its asynchronous nature and channel independence.
- Deadlocks: Occur if you introduce dependencies between channels (e.g., waiting for BVALID before asserting RREADY).
- Ordering Violations: Ensuring interactions with the same ID complete in order, while different IDs can pass each other.
- 4K Crossing: Bursts cannot cross 4KB boundaries. This is the #1 bug in new AXI masters.
AHB Verification Challenges
AHB is simpler but has timing nuances.
- Early Burst Termination: Masters typically can't cancel a burst easily once started, unlike AXI's precise control.
- Retry/Split Responses: Legacy AHB slaves responding with RETRY can stall the bus efficiently but are tricky to verify.
Why do we still use APB?
You might ask, "If AXI is so fast, why use APB?"
- Area & Power: AXI requires massive routing resources (5 channels, IDs, Len, Size). APB is just Address, Data, Enable, Select.
- Simplicity: Configuration registers don't need high bandwidth. They are accessed once at boot. Complexity here is a waste.
- Timing: Closing timing on a massive AXI crossbar is hard. APB bridges allow you to step down frequency easily.
Interview Questions
Q: Why does AXI have separate Read/Write address channels, but AHB shares
one?
AXI allows Full Duplex communication. A master can issue a Read Address and
a Write Address simultaneously, doubling theoretical throughput. AHB is a shared bus; you
are either writing OR reading.
Q: Can an APB bridge handle an AXI burst?
Not directly. The bridge acts as a "shim". It accepts the AXI burst, buffers it, and
executes single APB transfers for each beat. This is why accessing APB registers via AXI is
slow (multi-cycle latency per beat).