AXI Burst Types & Unaligned Access

AXI supports versatile burst modes and handles unaligned start addresses automatically.

AXI Burst Types at a Glance

Bursts	Enc.	Use Case
`FIXED`	`00`	FIFO access, repetitive addr
`INCR`	`01`	Normal memory, block copy
`WRAP`	`10`	Cache line fills (power of 2)

Why use Bursts? (The Laundry Analogy)

Imagine you have a basket full of dirty laundry. You could take one sock to the washing machine, wait for it to wash, come back, take another sock, and repeat. This would take forever because you're spending all your time walking back and forth.

In AXI, a Burst is like taking the whole basket at once. You send one "Address" (the destination) and then follow it with many "Data" packets. This is much faster because the computer doesn't have to keep asking "Where is this going?" for every single piece of data.

The Burst Family: FIXED, INCR, and WRAP

AXI has three main ways of moving this "basket" of data. Think of them as different ways to walk down a street of houses (memory addresses):

FIXED (The Post Office Box): You keep going to the same house over and over. This is used for special hardware called FIFOs where all data is read from one single spot.
INCR (The Delivery Driver): You start at House #1, then move to House #2, House #3, and so on. This is the most common way to move large blocks of data in memory.
WRAP (The Track and Field): You run in a loop. If the track is 16 meters long and you start at meter 12, you go 13, 14, 15, and then wrap back to meter 0. This is used by CPUs to fill their "Caches" extremely efficiently.

Pro Tip: WRAP Boundaries

Wrapping bursts only work in sizes that are powers of 2 (2, 4, 8, or 16). Hardware engineers love powers of 2 because the math can be done by just "masking" bits, which is nearly instant.

Unaligned Access: Starting in the Middle

Usually, memory is organized in "Words" (like 4-byte or 8-byte blocks). Most protocols require you to start at the beginning of a word (Address 0, 4, 8, etc.).

AXI is different. It allows you to start at any address (like Address 1 or 3). This is called "Unaligned Access."

// Example: 4-byte Word, but you start at Address 0x1
Beat 1: Read Address 0x1 (Hardware uses "Strobes" to ignore byte 0)
Beat 2: Read Address 0x4 (Hardware automatically aligns back to the boundary)
Beat 3: Read Address 0x8

This makes life very easy for software programmers, but it makes the hardware design a bit more complex!

4KB Boundary: The Invisible Wall

The most famous rule in AXI is: "Thou shalt not cross a 4KB boundary in a single burst."

Think of 4KB as a Border Crossing. On one side of the border might be your RAM, and on the other side might be your Graphic Card.

If a burst crossed the boundary, it might accidentally start writing data to the Graphics Card when it was supposed to be writing to RAM.
The system can't check permissions "mid-burst," so it's safer to just forbid crossing entirely. If you need to send 8KB of data, you must send two separate bursts.

Common Interview Questions

Why does AXI WRAP burst not support Length 3?

Wrapping bursts are designed to align to address boundaries that are powers of 2 (2, 4, 8, 16 beats). The wrap boundary calculation uses simple bitwise masking: Wrap_Boundary = Start_Addr & ~(Total_Bytes - 1). This efficiency relies on `Total_Bytes` being a power of 2. Supporting Length 3 would require complex modulo arithmetic in hardware, violating the protocol's goal of high-speed simplicity.

What is the 4KB Boundary rule?

A single burst must not cross a 4KB address boundary to prevent crossing into a different physical page or slave peripheral region, which could cause system faults.

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