| 00 | FIXED | Address remains constant (used for FIFOs). |
| 01 | INCR | Incrementing address (Normal memory access). |
| 10 | WRAP | Wraps at boundary (Cache line fills). |
AXI Burst Types & Unaligned Access
AXI supports versatile burst modes and handles unaligned start addresses automatically.
AXI Burst Types at a Glance
| Bursts | Enc. | Use Case |
|---|---|---|
FIXED |
00 |
FIFO access, repetitive addr |
INCR |
01 |
Normal memory, block copy |
WRAP |
10 |
Cache line fills (power of 2) |
Burst Types (AxBURST)
Unaligned Access
AXI Masters can issue a start address that is NOT aligned to the transfer size.
// Example: 32-bit transfer (Size=4 bytes), Start Address = 0x1 (Not 0x0/0x4)
// The first beat will drive 0x1.
// The next beat will force alignment -> 0x4.
// Subsequent beats increment by 4: 0x8, 0xC, etc.Slaves must handle this. Typically, the Master uses the Write Strobe (WSTRB) signals to indicate which bytes are valid in the unaligned first transfer.
4KB Boundary Rule
Critical Restriction
An AXI burst must NEVER cross a 4KB address boundary.
Why 4KB? Because virtual memory pages are typically 4KB. If a burst crosses 4KB, it might cross from a valid physical page to an invalid one (Page Fault), or from Device A to Device B. The interconnect cannot easily check address permissions mid-burst.
Common Interview Questions
Why does AXI WRAP burst not support Length 3?
Wrapping bursts are designed to align to address boundaries that are
powers of 2 (2, 4, 8, 16 beats). The wrap boundary calculation uses
simple bitwise masking:
Wrap_Boundary = Start_Addr & ~(Total_Bytes - 1).
This efficiency relies on `Total_Bytes` being a power of 2. Supporting Length 3 would
require complex modulo arithmetic in hardware, violating the protocol's goal of
high-speed simplicity.
What is the 4KB Boundary rule?
A single burst must not cross a 4KB address boundary to prevent
crossing into a different physical page or slave peripheral region, which could cause
system faults.