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SPI Transactions

How data is actually moved between Master and Slave using shift registers.

The Shift Register Mechanism

Think of SPI as two circular conveyor belts. As the Master pushes one bit out (MOSI), it pulls one bit in (MISO) at the exact same time. It is a "Data Exchange" rather than just a "Write" or "Read".

Both the Master and the Slave contain a shift register (usually 8-bit or 16-bit). When the clock (sclk) pulses:

  1. Master shifts bit MSB out on MOSI line.
  2. Slave shifts bit MSB out on MISO line.
  3. Master samples MISO into LSB.
  4. Slave samples MOSI into LSB.

After 8 clock cycles, the Master's byte is in the Slave, and the Slave's byte is in the Master.

Multi-Slave Configurations

1. Independent Slave Configuration

This is the most common setup. The Master has dedicated Chip Select (CS) lines for each slave.

  • Master asserts CS1 (low) -> Communicates with Slave 1.
  • Master asserts CS2 (low) -> Communicates with Slave 2.

Addressing vs Selection

SPI does not send an "Address" byte to select a slave (unlike I2C). It physically selects them using wires. This makes it faster but requires more pins on the Master.

2. Daisy Chain Configuration

Slaves are connected in series: Master MOSI -> Slave1 MOSI -> Slave1 MISO -> Slave2 MOSI -> ...

This saves pins (only requires 1 CS line for all slaves) but is slower because data must propagate through all shift registers to reach the last device.

Common Interview Questions

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Why doesn't SPI have an ACK bit?

SPI is designed for speed and simplicity in hardware. Adding an ACK like I2C implies bidirectional checking and turn-around time, which slows down the continuous stream of data. The Master blindly assumes the Slave is listening if CS is low.

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How do you verify SPI?

Since it's synchronous:

  1. Check Protocol Compliance: Use SVA (SystemVerilog Assertions) to check if data changes on the correct edge relative to CPOL/CPHA.
  2. Check Data Integrity: Use a Scoreboard to compare the data sent by the Driver vs the data received by the Monitor.
  3. Corner Cases: Test back-to-back transfers, varying clock frequencies, and random delays between CS assertion and first clock edge.

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