SPI Modes (CPOL & CPHA)

Understanding Clock Polarity (CPOL) and Clock Phase (CPHA) is essential for configuring SPI devices correctly.

The Two Parameters

⚡ Interview Answer

SPI has 4 modes defined by two bits:

CPOL (Clock Polarity): Idle state of the clock. (0 = Low, 1 = High).
CPHA (Clock Phase): Sampling edge. (0 = First Edge, 1 = Second Edge).

Unlike I2C or UART which have fixed standards, SPI allows flexibility in how the data is synchronized with the clock.

The 4 Modes Table

Mode	CPOL	CPHA	Clock Idle State	Sample Data On
0	0	0	Low	Rising Edge (1st)
1	0	1	Low	Falling Edge (2nd)
2	1	0	High	Falling Edge (1st)
3	1	1	High	Rising Edge (2nd)

Visualizing the Modes

CPOL=0 (Modes 0 & 1)

CPOL=1 (Modes 2 & 3)

Mismatched Modes

If the Master is in Mode 0 and the Slave is in Mode 1, data will be sampled at the wrong time (setup/hold violations), leading to corrupted bits. Always ensure both devices share the same configuration.

Code Representation (Verilog)

In a generic SPI Controller RTL, you might see logic like this:

Generic SPI Sample Logic


always @(posedge clk) begin
    // Mode 0: CPOL=0, CPHA=0 -> Sample on Rising Edge of SCLK
    if (mode == 0 && sclk_rising) 
        sample_miso <= miso_in;
    // Mode 1: CPOL=0, CPHA=1 -> Sample on Falling Edge of SCLK
    else if (mode == 1 && sclk_falling)
        sample_miso <= miso_in;
    // ... logic for Mode 2 & 3
end

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