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SPI Daisy Chaining

Save board space and pins by connecting devices in series. One Chip Select to rule them all.

The Concept

Standard SPI requires a separate Chip Select (CS) line for every slave. If you have 10 slaves, you need 10 CS pins on your microcontroller.

Daisy Chaining allows you to drive ANY number of slaves using just One CS pin. It works by treating the entire chain of slaves as one giant Shift Register.

graph LR M[Master] -- MOSI --> S1[Slave 1] S1 -- MISO --> S2[Slave 2] S2 -- MISO --> S3[Slave 3] S3 -- MISO --> M M -- CS --> S1 M -- CS --> S2 M -- CS --> S3 M -- SCLK --> S1 M -- SCLK --> S2 M -- SCLK --> S3 style M fill:#f9f,stroke:#333

How It Works

Shift Propagation

Inside every SPI Slave is a shift register. In Daisy Chain mode:

  1. Master asserts CS (Low) for ALL slaves simultaneously.
  2. Master clocks out Data Byte 1, then Byte 2, then Byte 3.
  3. Byte 1 enters Slave 1. As Byte 2 enters Slave 1, Byte 1 is pushed out of Slave 1's MISO and enters Slave 2's MOSI.
  4. After 3 bytes of clocking, Byte 3 is in Slave 1, Byte 2 is in Slave 2, and Byte 1 is in Slave 3.
  5. Master de-asserts CS (High). All slaves latch their respective data simultaneously.

Latency Limitation

The downside is latency. To talk to Slave 3, you MUST send data for Slave 1 and Slave 2 as well (even if it's dummy data).

Design & Verification Considerations

  • CPOL/CPHA: All devices in the chain MUST share the same Clock Polarity and Phase settings.
  • Propagation Delay: The signal travels through the combinational logic of each slave. For very long chains or high speeds, the delay (T_prop) from S1_MOSI to S1_MISO might cause timing violations at S2.
  • Verification: Your testbench must model the full delay path and verify that the data correctly shifts through the entire chain without corruption.
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