Introduced in SystemVerilog-2012, Interface Classes solve the "Diamond Problem" and enable true Multiple Inheritance in testbenches.
SystemVerilog, like Java, only allows a class to extend one parent class (`extends Base`). But what if you want a `Driver` to be both a `Component` AND a `PacketListener`?
Interface Class is the solution. It defines a contract (a set of pure virtual methods) that a class must implement. A class can implement multiple interface classes.
implements an interface class.Imagine you are building a generic Scoreboard that can handle any protocol, as long as the protocol object supports a `compare()` method.
// 1. Define the Interface Class
interface class Comparable;
pure virtual function bit compare(Comparable other);
endclass
// 2. Implement it in your Transaction
class Packet extends uvm_object implements Comparable;
int data;
// You MUST implement compare() or this class will be abstract
virtual function bit compare(Comparable other);
Packet p;
if (!$cast(p, other)) return 0; // Type safety check
return (this.data == p.data);
endfunction
endclass
Building a class that is both a Serializer and a Printer.
interface class Serializer;
pure virtual function bits[] pack();
endclass
interface class Printer;
pure virtual function void print();
endclass
// Implements BOTH
class MyData implements Serializer, Printer;
int a = 5;
virtual function bits[] pack();
return { >> {a} };
endfunction
virtual function void print();
$display("Data: %d", a);
endfunction
endclass
interface class B extends A;. This builds a hierarchy of contracts.