Basic Data Types in SystemVerilog

This is the most fundamental distinction in SystemVerilog data types. Understanding it is essential!

4-State Types (From Verilog)

Can hold four values: 0, 1, X (unknown), Z (high impedance)

• reg - Original Verilog register type
• logic - SystemVerilog replacement for reg and wire
• integer - 32-bit signed, 4-state
• time - 64-bit unsigned for simulation time

2-State Types (New in SystemVerilog)

Can only hold: 0 and 1. Faster simulation, less memory!

• bit - Single bit (unsigned)
• byte - 8 bits signed
• shortint - 16 bits signed
• int - 32 bits signed
• longint - 64 bits signed

// 4-state: Can detect X/Z from RTL
logic [7:0] rtl_data;        // Use in RTL, can be X or Z
wire [7:0] data_bus;         // Tri-state bus
// 2-state: Faster, use in testbench when you don't need X/Z
bit [7:0] tb_data;           // Testbench variables
int counter;                 // Loop counters
bit [31:0] expected_value;   // Reference model values
// Important: 2-state defaults to 0, not X!
bit    b;     // Initialized to 0
logic  l;     // Initialized to X
// Converting 4-state to 2-state
logic [7:0] from_rtl = 8'b1010_xxxx;
bit [7:0]   in_tb = from_rtl;  // X becomes 0: 8'b1010_0000
                                // WARNING: Silent conversion!

When to Use Which?

By default, bit and logic are unsigned. Use the signed keyword when you need signed arithmetic.

// Unsigned (default)
bit [7:0] unsigned_val = 8'hFF;  // Value: 255
// Signed
bit signed [7:0] signed_val = 8'hFF;  // Value: -1
// Pre-defined signed types
byte      b = -10;    // 8-bit signed
shortint  s = -1000;  // 16-bit signed  
int       i = -50000; // 32-bit signed
longint   l = -1;     // 64-bit signed
// Mixing signed and unsigned - CAREFUL!
logic [3:0] a = 4'b1111;           // 15 (unsigned)
logic signed [3:0] b = 4'b1111;   // -1 (signed)
int result1 = a;  // Result: 15
int result2 = b;  // Result: -1 (sign extended)
// Comparison gotcha
if (a > b) $display("a > b");  // True! 15 > -1
// But if both were unsigned:
logic [3:0] c = 4'b1111;
logic [3:0] d = 4'b1111;
if (c > d) $display("c > d");  // False, they're equal

SystemVerilog has a built-in string type for dynamic text handling. Much easier than Verilog's character arrays!

// Declaration and initialization
string name = "AHB_Transaction";
string empty_string;  // Empty by default
// String methods
string s = "Hello, VLSI World!";
$display("Length: %0d", s.len());           // 18
$display("Upper: %s", s.toupper());         // HELLO, VLSI WORLD!
$display("Lower: %s", s.tolower());         // hello, vlsi world!
$display("Char at 7: %s", s.getc(7));       // V
// Substring
string sub = s.substr(7, 10);  // "VLSI"
// Comparison
string a = "abc";
string b = "abd";
if (a < b) $display("a comes before b");  // Lexicographic
// Concatenation
string first = "Hello";
string last = "World";
string full = {first, " ", last};  // "Hello World"
// Formatting
int addr = 32'h1000;
string msg = $sformatf("Address: 0x%08h", addr);
// Convert to/from integer
string num_str = "12345";
int num = num_str.atoi();  // 12345
int value = 9876;
string val_str;
val_str.itoa(value);  // "9876"
// Useful in testbenches
function void print_transaction(string name, int addr, int data);
    $display("[%s] ADDR=0x%08h, DATA=0x%08h", name, addr, data);
endfunction

Think of a standard light switch. It can be On (1) or Off (0). This is exactly how the bit type works in SystemVerilog. It's simple and fast.

But in the world of high-end chip design, things can go wrong. That's why we have logic (the 4-state type). It adds two more options:

• X (The "I'm Broken" State): This happens when your hardware is confused. Maybe two different parts are trying to turn the light on and off at the same time.
• Z (The "Disconnected" State): This is like physically removing the light switch. The wire is just floating there, not connected to anything.

Imagine you have $0 in your bank account, and you spend $1.

• Unsigned (The 8'hFF): The computer doesn't understand "negative." It wraps around and suddenly tells you that you have **$255**! (In binary, `00000000` becomes `11111111`).
• Signed (The -1): The computer understands debt. It correctly tells you that you have **-$1**.

In SystemVerilog, types like byte, int, and longint are "Signed" by default. This makes them perfect for math where numbers can go below zero.

Would you rather tell your friend: "Hey, call 555-0123-9876" or "Hey, call John"?

typedef is exactly like giving a nickname to a long, complex name. Instead of typing bit [63:0] every time you want to talk about a memory address, you can just do this once:

typedef bit [63:0] addr_t; // "addr_t" is now the nickname for bit [63:0]
addr_t my_address; // So much cleaner!

Enums are another way to keep your code human-friendly. Instead of using "Magic Numbers" like 0, 1, and 2, you use real names:

typedef enum {IDLE, READ, WRITE} state_t;
state_t current_state = IDLE; // Anyone reading this understands what it means!

Using Enums is like using names in your phone's contact list instead of memorizing everyone's phone number.

typedef creates new type names, making code cleaner and more maintainable.

// Create type aliases
typedef bit [31:0] addr_t;
typedef bit [63:0] data_t;
typedef logic [7:0] byte_t;
// Use them
addr_t address;
data_t data;
// For parameterized types
typedef byte_t memory_t [0:1023];  // Array of 1024 bytes
memory_t my_memory;
// Complex typedef
typedef struct packed {
    bit [31:0] addr;
    bit [31:0] data;
    bit [3:0]  be;
    bit        write;
} transaction_t;
transaction_t txn;
txn.addr = 32'h1000;
txn.data = 32'hDEADBEEF;
txn.be = 4'b1111;
txn.write = 1;
// Forward declaration (for recursive structures)
typedef class my_class;
class another_class;
    my_class ref_to_my_class;
endclass
class my_class;
    another_class ref_to_another;
endclass

1. What is the difference between logic and reg?

   Functionally they're similar (both 4-state), but logic can be driven by both continuous assignment and procedural blocks, while reg is only for procedural. In modern SystemVerilog, use logic everywhere in RTL.

2. When should you use bit vs logic in testbench?

   Use bit for testbench variables where you don't need X/Z detection (transactions, counters). Use logic when sampling signals from DUT where you might need to detect undefined values.

3. What happens when you assign X to a bit type?

   X (and Z) silently converts to 0. This can hide bugs! Always check RTL outputs with logic type first.

4. What's the advantage of typedef?

   Code readability, consistent type usage across files, easier to change types globally, and self-documenting code.