Reference Model (ISS)

An Instruction Set Simulator (ISS) is a C/C++ program that implements the RISC-V specification exactly. It takes an elf file (binary) and executes it instruction by instruction, updating the architectural state (registers and memory).

• Spike: The official RISC-V golden reference model.
• Whisper: Developed by Western Digital for the SweRV Core. Good for interactive debug.
• OVPsim: Commercial grade simulator from Imperas.

This is the most robust verification method, also known as Lock-step Simulation.

1. Run RTL: Execute one instruction. Capture the commit (register write).
2. Run ISS: Execute the same instruction in the C++ model.
3. Compare: Check if RTL.PC == ISS.PC and RTL.RegWrite == ISS.RegWrite.
4. Error: Stop immediately if they mismatch.

DPI-C Integration Example

We use SystemVerilog DPI to call the C++ ISS functions from UVM.

// Import C++ functions
import "DPI-C" function void iss_step(input int instr);
import "DPI-C" function int iss_get_reg(input int reg_idx);
class riscv_scoreboard extends uvm_scoreboard;
    function void write_rtl_complete(transaction tr);
        // 1. Step the ISS reference model with the same instruction
        iss_step(tr.instruction_word);
        // 2. Get Expected Result (Golden)
        int expected_val = iss_get_reg(tr.rd_addr);
        // 3. Compare with RTL
        if (tr.rd_val !== expected_val) begin
            `uvm_fatal("MISMATCH", $sformatf("Instr: %h | RTL: %h | ISS: %h", 
                                             tr.instruction_word, tr.rd_val, expected_val))
        end else begin
            `uvm_info("MATCH", "Instruction executed correctly", UVM_HIGH)
        end
    endfunction
endclass