RV32I ISA Basics

The foundation of RISC-V verification is understanding the instruction formats and register set of the base integer ISA (RV32I).

Register File (RV32I)

RV32I has 32 general-purpose 32-bit registers. While hardware treats most identically (except x0), the software Application Binary Interface (ABI) assigns specific roles.

Register	ABI Name	Description	Saver
x0	zero	Hardwired to 0. Writes are discarded.	-
x1	ra	Return Address for function calls.	Caller
x2	sp	Stack Pointer.	Callee
x3	gp	Global Pointer.	-
x4	tp	Thread Pointer.	-
x5-x7, x28-x31	t0-t6	Temporaries.	Caller
x8-x9, x18-x27	s0-s11	Saved Registers.	Callee
x10-x17	a0-a7	Function Arguments / Return Values.	Caller

Instruction Formats

RISC-V uses a fixed 32-bit length for standard instructions, aligned on 4-byte boundaries. The ISA is designed for simple hardware decoding: the opcode is always in the same location.

R-Type (Register-Register)

Used for arithmetic computations like ADD, SUB, SLL.


| 31 ... 25 | 24 ... 20 | 19 ... 15 | 14 ... 12 | 11 ... 7 | 6 ... 0 |
|   funct7  |    rs2    |    rs1    |  funct3   |    rd    |  opcode |

I-Type (Immediate)

Used for arithmetic with constants (ADDI) and Loads (LW).


| 31 ................. 20 | 19 ... 15 | 14 ... 12 | 11 ... 7 | 6 ... 0 |
|      imm[11:0]          |    rs1    |  funct3   |    rd    |  opcode |

S-Type (Store)

Used for Stores (SW, SB). Note that the immediate is split!


| 31 ... 25 | 24 ... 20 | 19 ... 15 | 14 ... 12 | 11 .... 7 | 6 ... 0 |
| imm[11:5] |    rs2    |    rs1    |  funct3   | imm[4:0]  |  opcode |

Verification Tip: Misaligned memory accesses (e.g., storing a word at address 0x1001) may trigger a trap depending on the core implementation. Always randomize addresses with legal alignment constraints initially.

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