| Trigger | Description | Example |
|---|---|---|
Timer(time, units) |
Wait for a fixed simulation time. | await Timer(10, 'ns') |
RisingEdge(signal) |
Wait for signal to go from 0 -> 1. | await RisingEdge(dut.clk) |
FallingEdge(signal) |
Wait for signal to go from 1 -> 0. | await FallingEdge(dut.clk) |
ReadOnly() |
Wait until all delta cycles are done (Postponed region). Safe for checking values. | await ReadOnly() |
Cocotb Triggers
Triggers are the mechanism to pause a coroutine until a specific event occurs in the simulator. They are the standard way to synchronize Python with Verilog.
Common Triggers
Combining Triggers
Sometimes you want to wait for "This OR That". Use First().
from cocotb.triggers import RisingEdge, Timer, First
# Wait for clock edge OR a timeout (whichever happens first)
edge = RisingEdge(dut.clk)
timeout = Timer(100, "ns")
t_fired = await First(edge, timeout)
if t_fired == timeout:
print("Timed out waiting for clock!")