from cocotb_test.simulator import run
import pytest
@pytest.mark.parametrize("width", [8, 16, 32])
def test_adder(width):
run(
verilog_sources=["adder.sv"],
toplevel="adder", # Name of Verilog module
module="test_adder", # Name of Python test file
parameters={"WIDTH": str(width)},
sim_build=f"sim_build/run_{width}"
)
Run this with a simple command: pytest test_runner.py.
Bonus: Traditional Makefile Snippet
If you prefer the traditional Cocotb flow, here is a clean `Makefile` template:
SIM ?= icarus
TOPLEVEL_LANG ?= verilog
VERILOG_SOURCES += $(PWD)/my_design.sv
TOPLEVEL = my_design
MODULE = my_test
include $(shell cocotb-config --makefiles)/Makefile.sim