RX Filtering & Sampling

A real-world UART receiver doesn't just look for a falling edge. It uses oversampling to reject noise. Only senior engineers know this level of detail.

The Noise Problem

In an industrial environment, the RX line might pick up a spike (glitch) that looks like a Start Bit (High -> Low).

If the UART Receiver triggers on a simple `negedge`, it will read garbage data. To prevent this, standard IPs (like the 16550) use 16x Oversampling.

16x Oversampling Logic

The receiver clock runs at 16 times the Baud Rate. For every bit period, the RX counts 16 ticks.

1. Start Bit Detection (Majority Vote)

When the RX line drops Low, the receiver doesn't trust it immediately. It checks the samples at ticks 7, 8, and 9 (the middle of the bit).

If Ticks 7,8,9 are ALL Low -> Valid Start Bit.
If Ticks 7,8,9 are Mixed/High -> Glitch! Return to Idle.

2. Data Bit Sampling

For every subsequent data bit, the receiver waits 16 ticks to reach the center of the next bit. Again, it samples pulses 7, 8, and 9.

2 or more Highs -> Logic 1.
2 or more Lows -> Logic 0.

RTL Representation

Verilog Glitch Filter (Simplified)


reg [3:0] sample_cnt;
reg [7:0] shift_reg;
always @(posedge clk_16x) begin
    case (state)
        IDLE: begin
            if (rx_in == 0 && sample_cnt == 7) begin
                // Check middle of Start Bit
                if (vote(samples[7:9]) == 0) 
                    state <= DATA_BITS;
                else 
                    sample_cnt <= 0; // False alarm (Glitch)
            end
            else if (rx_in == 0)
                sample_cnt <= sample_cnt + 1;
            else
                sample_cnt <= 0;
        end
        // ...
    endcase
end

Clock Drift Tolerance

Oversampling also helps with clock mismatch. If the TX is 2% faster than RX:

Bit 0: Sampled at tick 8 (Center).
Bit 8: Might be sampled at tick 9 or 10.

As long as the sampling point (the "eye") is within the stable region (ticks 5-11), the data is recovered correctly. This allows UART to tolerate up to ~5% error without specific clock synchronization.

Previous Baud Rate Generation