Code Coverage Types

Code Coverage is your first line of defense in verification. It tells you which lines, branches, and states your testbench has physically executed. While it doesn't prove correctness, it highlights what you haven't tested.

The Big 4 Coverage Types

Most simulators (VCS, Questa, Xcelium) provide these standard metrics automatically.

1. Line / Block Coverage

Did the simulator execution flow pass through this specific line?

if (reset) begin
    count <= 0;   // Lines checked green are covered
end else begin
    count <= count + 1; // Red lines = dead code or missing test
end

Goal: 100%. If you can't hit a line, it's either dead code (delete it) or a bug in your test plan.

2. Toggle Coverage

Did every bit of a signal flip 0→1 and 1→0?

Target: Every wire, register, and port.
Why: Catch "Stuck-at" faults or unconnected wires.
Example: A 32-bit address bus where bit[31] never goes high suggests you aren't testing high memory addresses.

3. Expression / Condition Coverage

Checking all permutations of logic conditions.

if (A && B && C) ...

Line coverage counts this as "covered" if it executes once.
Condition coverage demands you test:

A=0, B=x, C=x
A=x, B=0, C=x
A=1, B=1, C=1

4. FSM Coverage

Automatic extraction of State Machines.

State Coverage: Were IDLE, BUSY, ERROR states reached?
Arc Coverage: Did we transition IDLE->BUSY and BUSY->IDLE?

When to use what?

Metric	What it catches	Urgency
Line Coverage	Unreachable code, missing basic features
Toggle	Unconnected ports, stuck logic
Condition	Complex logic bugs, edge cases in IFs	Medium

Functional vs Code Coverage

This is the most common interview question in verification.

Code Coverage asks: "Did the code execute?"

Functional Coverage asks: "Did the design do what the specs said?"

Example: You can have 100% Line Coverage on a FIFO, but 0% Functional Coverage if you never tested the "FIFO Full" condition because you forgot to write a test for it.

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