Matches when two sequences start at the same time AND end at the same time.
// Check that 'burst_write' sequence happens exactly during 'enable_window'
sequence s_burst;
req ##1 ack ##1 data[*4]; // Length = 6
endsequence
property p_intersect;
@(posedge clk) start_burst |-> (s_burst intersect enable_window);
endproperty
- Requirement: Length(Seq1) must equal Length(Seq2).
- Use Case: Verifying that a packet transfer completes precisely before a timer expires.