I2C Protocol & Handshake

Unlike normal data bits, Start and Stop are unique patterns where SDA changes while SCL is HIGH.

• Start (S): SDA goes High -> Low while SCL is High.
• Stop (P): SDA goes Low -> High while SCL is High.
• Data Validity: During normal data transfer, SDA must remain stable when SCL is High. It can only change when SCL is Low.

1. Start Condition
2. Address (7 bits): MSB first.
3. R/W Bit: 0 = Write to Slave, 1 = Read from Slave.
4. ACK/NACK (from Slave): Slave pulls SDA Low to ACK.
5. Data Byte (8 bits): Sent by Master (if Write) or Slave (if Read).
6. ACK/NACK: Receiver acknowledges.
7. Stop Condition

I2C allows the Slave to pause the Master by holding the Clock (SCL) line LOW. This is a unique feature of I2C compared to SPI or UART.

When is it used?

• ADC/Sensors: An ADC might need time to convert an analog signal before it has the data ready to send. It holds SCL Low during the "Read" phase until the conversion is done.
• Microcontrollers: If a Slave MCU receives a byte but hasn't cleared its RX buffer interrupt yet, it holds SCL Low to prevent the Master from sending the next byte.

The Mechanism

I2C is Open-Drain. The SCL line is the logical AND of all devices.
1. Master releases SCL (High) to generate a clock pulse.
2. But Slave pulls SCL Low.
3. Master reads SCL pin. It sees LOW.
4. Master enters a Wait State. It will not drive the next edge until SCL naturally rises to High.